EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 510

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–66
Stratix IV Device Handbook Volume 2: Transceivers
In some Basic single-width configurations with a 10-bit PMA-PCS interface, you can
configure the word aligner in bit-slip mode by selecting the Use manual bit slipping
mode option in the ALTGX MegaWizard Plug-In Manager.
The word aligner operation for Basic single-width with a 10-bit PMA-PCS interface is
similar to the word aligner operation in Basic single-width mode with an 8-bit
PMA-PCS interface. For word aligner operation in bit-slip mode, refer to
Alignment Mode Word Aligner with 8-Bit PMA-PCS Interface Modes” on page
The only difference is that the bit-slip word aligner with 10-bit PMA-PCS interface
modes allows 7-bit and 10-bit word alignment patterns, whereas the one with 8-bit
PMA-PCS interface modes allows only 16-bit word alignment patterns.
In double-width mode, the PMA-PCS interface is either 16 or 20 bits wide. In 16-bit
PMA-PCS interface modes, the word aligner receives 16 bit wide data from the
deserializer. In 20-bit PMA-PCS interface modes, the word aligner receives 10-bit
wide data from the deserializer. Depending on the configured functional mode, you
can configure the word aligner in manual alignment mode or bit-slip mode.
Automatic synchronization state machine mode is not supported for word aligner in
double-width mode.
The following functional modes support the 16-bit PMA-PCS interface:
■
■
■
Table 1–29
16-bit PMA-PCS interface.
Table 1–29. Word Aligner Configurations with 16-Bit PMA-PCS Interface
In manual alignment mode, the word aligner starts looking for the programmed 8-bit,
16-bit, or 32-bit word alignment pattern in the received data stream as soon as
rx_digitalreset is de-asserted low. It aligns to the first word alignment pattern
received regardless of the logic level driven on the rx_enapatternalign signal. Any
word alignment pattern received thereafter in a different word boundary does not
cause the word aligner to re-align to this new word boundary. After the initial word
alignment following de-assertion of the rx_digitalreset signal, if a word
re-alignment is required, you must use the rx_enapatternalign signal.
SONET/SDH OC-96
Basic double-width
Note to
(1) The word aligner is bypassed in (OIF) CEI PHY interface mode.
SONET/SDH OC-96
(OIF) CEI PHY interface
Basic double-width
Word Aligner in Double-Width Mode
Functional Mode
Table
Bit-Slip Mode Word Aligner with 10-Bit PMA-PCS Interface Mode
Word Aligner in Double-Width Mode with 16-Bit PMA-PCS Interface Modes
Manual Alignment Mode Word Aligner with 16-Bit PMA-PCS Interface Modes
lists the word aligner configurations allowed in functional modes with a
1–29:
Manual alignment, Bit-slip
Allowed Word Aligner
Manual alignment
Configurations
Chapter 1: Transceiver Architecture in Stratix IV Devices
February 2011 Altera Corporation
Allowed Word Alignment
8 bits, 16 bits, 32 bits
Transceiver Block Architecture
Pattern Length
16 bits, 32 bits
(Note 1)
“Manual
1–60.