EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 822

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

4–16
Table 4–6. Reset and Power-Down Sequences for Bonded Channel Configurations (Part 2 of 2)
Figure 4–8. Sample Reset Sequence of Receiver Only Channel—Receiver CDR in Automatic Lock Mode
Note to
(1) For t
Stratix IV Device Handbook Volume 2: Transceivers
Receiver and Transmitter
Receiver and Transmitter
Output Status Signals
Figure
Channel Set Up
LTD_Auto
Reset Signals
rx _ analogreset
rx _ digitalreset
rx _ freqlocked
4–8:
duration, refer to the
1
busy
Follow the same reset sequence for all the other channels in the non-bonded
configuration.
Transmitter Only Channel
This configuration contains only a transmitter channel. If you create a Transmitter
Only instance in the ALTGX MegaWizard Plug-In Manager, use the same reset
sequence shown in
Receiver Only Channel—Receiver CDR in Automatic Lock Mode
This configuration contains only a receiver channel. If you create a Receiver Only
instance in the ALTGX MegaWizard Plug-In Manager with the receiver CDR in
automatic lock mode, use the reset sequence shown in
Automatic lock mode
Manual lock mode
DC and Switching Characteristics for Stratix IV Devices
Receiver CDR Mode
Two parallel clock cycles
1
Figure 4–3 on page
2
“Receiver and Transmitter Channel—Receiver CDR in
Automatic Lock Mode” on page 4–18
“Receiver and Transmitter Channel—Receiver CDR in
Manual Lock Mode” on page 4–20
Chapter 4: Reset Control and Power Down in Stratix IV Devices
4–7.
3
t
LTD_Auto (1)
chapter.
4
Figure
Refer to
February 2011 Altera Corporation
4–8.
Transceiver Reset Sequences