EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 741
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Chapter 2: Transceiver Clocking in Stratix IV Devices
FPGA Fabric-Transceiver Interface Clocking
February 2011 Altera Corporation
User-Selected Receiver Phase Compensation FIFO Read Clock
The ALTGX MegaWizard Plug-In Manager provides an optional port named
rx_coreclk for each instantiated receiver channel. If you enable this port, the
Quartus II software does not automatically select the receiver phase compensation
FIFO read clock source. Instead, the signal that you drive on the rx_coreclk port of
the channel clocks the read side of its receiver phase compensation FIFO.
You can use the flexibility of selecting the receiver phase compensation FIFO read
clock to reduce the global, regional, or global and regional clock resource usage. You
can connect the rx_coreclk ports of all the receiver channels in your design and drive
them using a common clock driver that has a 0 PPM frequency difference with respect
to the FIFO write clocks of these channels. Use this common clock driver to latch the
receiver data and status signals in the FPGA fabric for these channels. This FPGA
fabric-Transceiver interface clocking scheme uses only one global, regional, or global
and regional clock resource for all channels.
Figure 2–37
serial data to all 16 channels has a 0 PPM frequency difference with respect to each
other. The rx_coreclk ports of all 16 channels are connected together and driven by a
common clock driver. This common clock driver also latches the receiver data and
status logic of all 16 receiver channels in the FPGA fabric. Only one global, regional, or
global and regional clock resource is used with this clocking scheme, compared to 16
global, regional, or global and regional clock resources needed without the
rx_coreclk ports (the Quartus II software-selected receiver phase compensation FIFO
read clock).
Example 8: Sixteen Identical Channels Across Four Transceiver Blocks
shows 16 channels located across four transceiver blocks. The incoming
Stratix IV Device Handbook Volume 2: Transceivers
2–69
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