EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 726

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

2–54
Figure 2–29. FPGA Fabric-Transmitter Interface Clocking for Example 3
Note to
(1) The green lines represent the low-speed parallel clock and the blue lines represent the high-speed serial clock.
Stratix IV Device Handbook Volume 2: Transceivers
Figure
and Control
and Control
and Control
and Control
Channel 3
Channel 1
Channel 0
Channel 2
TX Data
TX Data
TX Data
TX Data
Logic
Logic
Logic
Logic
2–29:
FPGA
Fabric
tx_coreclk[0]
tx_coreclk[2]
tx_coreclk[1]
tx_coreclk[3]
Figure 2–29
tx_clkout[2]
tx_clkout[0]
Reference
shows the FPGA fabric-Transmitter interface clocking for Example 3.
Reference
Clock
Clock
Input
Input
CMU1 PLL
Compensation
Compensation
Compensation
CMU0 PLL
Compensation
wrclk
wrclk
wrclk
wrclk
TX Phase
TX Phase
TX Phase
TX Phase
FIFO
FIFO
FIFO
FIFO
rdclk
rdclk
rdclk
rdclk
DIvider
CMU1
DIvider
Clock
CMU0
Clock
/2
/2
/2
/2
(Note 1)
Chapter 2: Transceiver Clocking in Stratix IV Devices
Low-Speed Parallel Clock
Low-Speed Parallel Clock
Low-Speed Parallel Clock
Low-Speed Parallel Clock
Transmitter Channel PCS
Transmitter Channel PCS
Transmitter Channel PCS
Transmitter Channel PCS
CMU1 Channel
CMU0 Channel
FPGA Fabric-Transceiver Interface Clocking
February 2011 Altera Corporation
Channel 3
Channel 1
Channel 0
Channel 2
Transmitter Channel PMA
Transmitter Channel PMA
Transmitter Channel PMA
High-Speed Serial Clock
Transmitter Channel PMA
Divider Block
Divider Block
Divider Block
Divider Block
Local Clock
Local Clock
Local Clock
Local Clock