EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 645

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Stratix IV Devices
Calibration Blocks
Table 1–70. Differences Between the 10G ATX PLL, 6G ATX PLL, and CMU PLL (Part 2 of 2)
Calibration Blocks
February 2011 Altera Corporation
Power Supply—V
options for PLLs
Phase noise
Notes to
(1) Using the L dividers available in ATX PLLs.
(2) For improved jitter performance, Altera strongly recommends using the refclk pins of the transceiver block located immediately below the 10G
(3) For more information, refer to the Input Reference Clock Source table in the
(4) Option in Stratix IV GT devices.
(5) For more information about phase noise and PLL bandwidths of ATX and CMU PLLs, refer to the characterization reports.
Difference Category/PLLs
ATX PLL block to drive the input reference clock.
Table
Calibration Block Location
1–70:
CCA_L/R
Stratix IV GX and GT devices contain calibration circuits that calibrate the OCT
resistors and the analog portions of the transceiver blocks to ensure that the
functionality is independent of process, voltage, or temperature variations.
Figure 1–167
different Stratix IV GX and GT devices. In
calibration block R0 and L0 refer to the calibration blocks on the right and left side of
the devices, respectively.
Figure 1–167. Calibration Block Locations in Stratix IV GX and GT Device with Two Transceiver
Blocks (on Each Side)
(V)
Lower when compared
with the CMU PLL
10G ATX PLL
shows the location and number of calibration blocks available for
2K
3.3
Ω
ATX PLL L0
Calibration
(5)
Block L0
GXBL1
GXBL0
Lower when compared with the
Stratix IV GX and GT
Stratix IV Transceiver Clocking
CMU PLL
6G ATX PLL
Device
3.3
Figure 1–167
3.0 or
(4)
(5)
Stratix IV Device Handbook Volume 2: Transceivers
ATX PLL R0
Calibration
GXBR0
Block R0
GXBR1
through
chapter.
Higher when compared with
Figure
the ATX PLLs
2K
Ω
CMU PLL
3.3
2.5 or
3.0 or
1–172, the
(4)
(5)
1–201