EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 715

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 2: Transceiver Clocking in Stratix IV Devices
Transceiver Channel Datapath Clocking
Table 2–10. Receiver Datapath Clock Frequencies in Non-Bonded Functional Modes with Rate Matcher
February 2011 Altera Corporation
PCIe ×1 (Gen 1)
PCIe ×1 (Gen 2)
GIGE
Serial RapidIO
Functional Mode
1
The parallel recovered clock from the receiver PMA in each channel clocks the word
aligner and the write port of the rate match FIFO. The low-speed parallel clock from
the transmitter local clock divider block in each channel clocks the read port of the
rate match FIFO, the 8B/10B decoder, and the write port of the byte deserializer (if
enabled). The parallel transmitter PCS clock or its divide-by-two version (if byte
deserializer is enabled) clocks the write port of the receiver phase compensation FIFO.
It is also driven on the tx_clkout port as the FPGA fabric-Transceiver interface clock.
You can use the tx_clkout signal to latch the receiver data and status signals in the
FPGA fabric.
Table 2–10
modes with rate matcher.
Bonded Channel Configurations
The Stratix IV device supports ×4 channel bonding that allows bonding of four
channels within the same transceiver block. It also supports ×8 channel bonding that
allows bonding of eight channels across two transceiver blocks on the same side of the
device.
In bonded channel configurations, the low-speed parallel clock for all bonded
channels are generated by the same CMU0 clock divider or the ATX clock divider block,
resulting in lower channel-to-channel clock skew. The receiver phase compensation
FIFO in all bonded channels (except in Basic [PMA Direct] ×N mode) share common
pointers and control logic generated in the CCU, resulting in equal latency in the
receiver phase compensation FIFO of all bonded channels.
Bonding is not supported on the receive side for Basic ×4 and Basic ×8 functional
modes. If you use rate matcher, the clocking scheme for Basic ×4 and Basic ×8
functional modes, the clocking is similar to PCIe ×4 mode, as shown in
page 2–46
×4 Bonded Channel Configuration
The following functional modes support ×4 receiver channel bonded configuration:
■
■
XAUI
PCIe
Data Rate
(Gbps)
3.125
1.25
1.25
2.5
2.5
5
(“x4 Bonded Channel Configuration Without Deskew FIFO” on page
(“x4 Bonded Channel Configuration with Deskew FIFO” on page
and PCIe ×8 mode, as shown in
lists the receiver datapath clock frequencies in non-bonded functional
Serial Recovered
Clock Frequency
1.5625 GHz
1.25 GHz
1.25 GHz
625 MHz
625 MHz
2.5 GHz
Transmitter PCS Clock
Parallel Recovered
Clock and Parallel
Frequency (MHz)
312.5
Figure 2–27 on page
250
500
125
125
250
Stratix IV Device Handbook Volume 2: Transceivers
Without Byte
Deserializer
Interface Clock Frequency
FPGA Fabric-Transceiver
(MHz)
250
N/A
125
N/A
N/A
N/A
2–48.
Figure 2–26 on
Deserializer
With Byte
2–44)
156.25
(MHz)
62.5
125
250
N/A
125
2–46)
2–43