EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 558

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–114
Figure 1–95. Transceiver Configurations in Basic Single-Width Mode with an 8-Bit PMA-PCS Interface for Stratix IV GT
Devices
Note to
(1) The maximum data rate specification shown in
Stratix IV Device Handbook Volume 2: Transceivers
other speed grades offered, refer to the
Figure
(1)
FPGA Fabric
Interface Frequency
(FPGA Fabric-Transceiver
(FPGA Fabric-Transceiver
(1)
Interface Clock Cycles)
Interface Clock Cycles)
Interface Frequency
Interface Frequency
TX PCS Latency
RX PCS Latency
Data Rate (Gbps)
1–95:
Low-Latency PCS
Channel Bonding
Rate Match FIFO
PMA-PCS/Fabric
Encoder/Decoder
Interface Width
(Pattern Length)
FPGA Fabric-
FPGA Fabric-
Interface Width
Byte Ordering
FPGA Fabric-
Transceiver
Transceiver
Transceiver
Word Aligner
Byte SerDes
Data Rate
PMA-PCS/Fabric
Interface Width
(MHz)
Functional
8B/10B
Modes
8-bit
Single
Width
Disabled
Manual Alignment
195 .3125
10-bit
155.5 –
16-bit
4 - 5.5
7 - 9
DC and Switching Characteristics
Disabled
Disabled
Enabled
(16-bit)
Basic
3.125
0.6 -
16-bit
Enabled
195.3125
4 - 5.5
155.5 –
16-bit
Figure 1–95
7 - 9
Double
Width
Disabled
20-bit
Stratix IV GT Configurations
is valid only for the -2 (fastest) speed grade devices. For data rate specifications for
Disabled
Disabled
Disabled
Enabled
195.3125
Bit-Slip
(16-bit)
4 - 5.5
155.5 –
16-bit
600 Mbps to 3.2 Gbps
3.125
0.6 -
7 - 9
Basic Single Width
8-bit PMA-PCS
Interface Width
x1, x4, x8
chapter.
10-bit
PIPE
Chapter 1: Transceiver Architecture in Stratix IV Devices
10-bit
XAUI
Protocol
SRIO
10-bit
SONET
/SDH
8-bit
16-bit
(OIF)
CEI
February 2011 Altera Corporation
Disabled
Disabled
Disabled
Disabled
Enabled
Enabled
0.6 - 3.2
16-bit
4 - 5.5
155.5 -
3 - 4.5
200
Transceiver Block Architecture
10-bit
SDI
10-Bit
Deterministic
Latency
20-Bit