EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 663

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Port Lists
Table 1–75. Stratix IV GX and GT ALTGX Megafunction Ports: CMU (Part 2 of 2)
Table 1–76. Stratix IV GX and GT ALTGX Megafunction Ports: Dynamic Reconfiguration (Part 1 of 2)
February 2011 Altera Corporation
pll_powerdown
coreclkout
reconfig_clk
Port Name
Port Name
Table 1–76
Output
Output
Output
Input/
Input
Input/
Input
lists the ALTGX megafunction dynamic reconfiguration ports.
DC and Switching
refer the device
Characteristics
Clock Domain
Asynchronous
requirements,
Clock Domain
For minimum
Clock signal
pulse width
Clock signal
chapter.
signal.
CMU PLL power down.
■
■
Note: Asserting the pll_powerdown signal does
not power down the REFCLK buffers.
FPGA fabric-transceiver interface clock.
■
■
■
■
■
Dynamic reconfiguration clock.
■
■
■
Asserted high—the CMU PLL is powered
down.
De-asserted low—the CMU PLL is active and
locks to the input reference clock.
Generated by the CMU0 clock divider in the
transceiver block in ×4 bonded channel
configurations.
Generated by the CMU0 clock divider in the
master transceiver block in ×8 bonded channel
configurations.
Not available in non-bonded channel
configurations.
Use to clock the write port of the transmitter
phase compensation FIFOs in all bonded
channels and to clock parallel data tx_datain
from the FPGA fabric into the transmitter
phase compensation FIFO of all bonded
channels.
Use to clock the read port of the receiver
phase compensation FIFOs in all bonded
channels with rate match FIFO enabled and to
clock parallel data rx_dataout from the
receiver phase compensation FIFOs of all
bonded channels (with rate match FIFO
enabled) into the FPGA fabric.
Also used for offset cancellation in all modes
except PCIe mode.
If configured in Transmitter only mode—the
frequency range is 2.5 MHz to 50 MHz.
If configured in Receiver only or Receiver
and Transceiver mode—the frequency
range of this clock is 37.5 MHz to 50 MHz.
Description
Description
Stratix IV Device Handbook Volume 2: Transceivers
Transceiver
Transceiver
Scope
Scope
block
block
1–219