EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 626
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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1–182
Figure 1–148. (OIF) CEI PHY Interface Mode Datapath
Figure 1–149. Transceiver Clocking in (OIF) CEI PHY Interface Mode
Stratix IV Device Handbook Volume 2: Transceivers
tx_coreclk
rx_coreclk
FPGA
Fabric
FPGA
Fabric-Transmitter
Interface Clock
FPGA
Fabric-Receiver
Interface Clock
(OIF) CEI PHY Interface Mode Datapath
Figure 1–148
in (OIF) CEI PHY interface mode.
Figure 1–149
Serial RapidIO Mode
The RapidIO Trade Association defines a high-performance, packet-switched
interconnect standard to pass data and control information between microprocessors,
digital signal, communications, and network processors, system memories, and
peripheral devices.
Serial RapidIO physical layer specification defines three line rates:
■
■
■
Transceiver Block Clocking with the
Use central clock divider to improve
transmitter jitter option disabled
1.25 Gbps
2.5 Gbps
3.125 Gbps
rx_clkout
CMU PLL
Compensation
Compensation
tx_clkout
wrclk
RX Phase
TX Phase
FIFO
FIFO
shows the ALTGX megafunction transceiver datapath when configured
shows transceiver clocking in (OIF) CEI PHY interface mode.
rdclk
Local Clock Divider Block
Local Clock Divider Block
Local Clock Divider Block
Local Clock Divider Block
wrclk
Serializer
/2
Byte
Ch 3
Ch 2
Ch 1
Ch 0
rdclk
Serializer
Parallel Recovered Clock
Byte
Low-Speed Parallel Clock
De-
Transmitter Channel PCS
/2
Receiver Channel PCS
Chapter 1: Transceiver Architecture in Stratix IV Devices
Channel 3
Channel 2
Channel 1
Channel 0
Serializer
Receiver Channel PMA
Transmitter Channel PMA
De-
Serializer
Divider
Clock
Local
February 2011 Altera Corporation
CDR
High-Speed Serial Clock
Transceiver Block Architecture
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