EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 248

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

7–28
Stratix IV Device Handbook Volume 1
Table 7–3. Possible Group Combinations in Stratix IV Devices (Part 2 of 2)
1517-Pin
FineLine BGA
1760-Pin
FineLine BGA
1932-Pin
FineLine BGA
Notes to
(1) Each side of the device in these packages has four remaining ×8/×9 groups. You can combine them for the write
(2) This device supports ×36 DQS/DQ groups on the top and bottom I/O banks natively.
(3) Although it is possible to combine the ×16/×18 DQS/DQ groups from I/O banks 1A and 1C, 2A and 2C, 5A and 5C,
Package
side (only) if you want to keep the ×36 QDR II+/QDR II SRAM interface on one side of the device. You must change
the Memory Interface Data Group default assignment from the default 18 to 9 in this case.
and 6A and 6C, Altera does not recommend this due to the size of the package. Similarly, crossing a bank number
(for example, combining groups from I/O banks 6C and 5C) is not supported in this package.
Table
7–3:
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
■
EP4SGX180
EP4SGX230
EP4SGX290
EP4SGX360
EP4SGX530
EP4SE530
EP4SE820
EP4S40G2
EP4S40G5
EP4S100G2
EP4S100G5
EP4SGX290
EP4SGX360
EP4SGX530
EP4SE530
EP4SE820
EP4SGX290
EP4SGX360
EP4SGX530
Device Density
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
1A and 1C, 2A and 2C (left I/O banks)
3A and 3B, 4A and 4B (bottom I/O banks)
5A and 5C, 6A and 6C (right I/O banks)
7A and 7B, 8A and 8B (top I/O banks)
1A and 1B, 2A and 2B or 1B and 1C, 2B and 2C (left I/O
banks)
5A and 5B, 6A and 6B or 5B and 5C, 6B and 6C (right I/O
banks)
3A and 3B, 4A and 4B (bottom I/O banks)
7A and 7B, 8A and 8B (top I/O banks)
1A and 1C, 2A and 2C (left I/O banks)
3A and 3B, 4A and 4B (bottom I/O banks)
5A and 5C, 6A and 6C (right I/O banks)
7A and 7B, 8A and 8B (top I/O banks)
1A and 1B, 2A and 2B or 1B and 1C, 2B and 2C (left I/O
banks)
5A and 5B, 6A and 6B or 5B and 5C, 6B and 6C (right I/O
banks)
1A and 1C, 2A and 2C (left I/O banks)
5A and 5C, 6A and 6C (right I/O banks)
Chapter 7: External Memory Interfaces in Stratix IV Devices
(3)
(3)
(3)
(3)
I/O Sub-Bank Combinations
February 2011 Altera Corporation
Memory Interfaces Pin Support