EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 448

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–4
Transceiver Channel Locations
Table 1–3. Number of Transceiver Channels and Transceiver Block Locations in Stratix IV GX Devices (Part 1 of 2)
Stratix IV Device Handbook Volume 2: Transceivers
EP4SGX70DF29
EP4SGX110DF29
EP4SGX180DF29
EP4SGX230DF29
EP4SGX290FH29
EP4SGX360FH29
EP4SGX110FF35
EP4SGX180FF35
EP4SGX230FF35
EP4SGX290FF35
EP4SGX360FF35
EP4SGX180HF35
EP4SGX230HF35
EP4SGX290HF35
EP4SGX360HF35
Device Member
Stratix IV GX Device Offerings
9.
10.
Stratix IV GX and GT transceivers are structured into full-duplex (Transmitter and
Receiver) four-channel groups called transceiver blocks. The total number of
transceiver channels and the location of transceiver blocks varies from device to
device.
Table 1–3
in each Stratix IV GX device member structured into full-duplex four- and six-channel
groups called transceiver blocks.
Total Number of
“Calibration Blocks” on page 1–201
“Built-In Self Test Modes” on page 1–206
Transceiver
Channels
16
24
8
lists the total number of transceiver channels and transceiver block locations
Eight transceiver channels located in two transceiver blocks:
■
Refer to
Eight transceiver channels located in two transceiver blocks:
■
■
Refer to
Eight regular transceiver channels supporting data rates between 600 Mbps
and 8.5 Gbps and four clock multiplier unit (CMU) channels supporting data
rates between 600 Mbps and 6.5 Gbps located in two transceiver blocks:
■
■
Refer to
Right side—GXBR0 and GXBR1
Right side—GXBR0 and GXBR1
Left side—GXBL0 and GXBL1
Right side—GXBR0 and GXBR1
Left side—GXBL0 and GXBL1
Figure 1–2 on page
Figure 1–2 on page
Figure 1–3 on page
Transceiver Channel Location
1–5.
1–5.
1–6.
Chapter 1: Transceiver Architecture in Stratix IV Devices
February 2011 Altera Corporation
Transceiver Channel Locations