EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 194

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

6–22
Stratix IV Device Handbook Volume 1
Programmable I/O Delay
Open-Drain Output
Bus Hold
f
f
The following sections describe programmable IOE delay and programmable output
buffer delay.
Programmable IOE Delay
The Stratix IV device IOE includes programmable delays, shown in
page
increase clock-to-output times. Each pin can have a different input delay from
pin-to-input register or a delay from output register-to-output pin values to ensure
that the bus has the same delay going into or out of the device. This feature helps read
and time margins because it minimizes the uncertainties between signals in the bus.
For more information about programmable IOE delay specifications, refer to the
and Switching Characteristics for Stratix IV Devices
Programmable Output Buffer Delay
Stratix IV devices support delay chains built inside the single-ended output buffer, as
shown in
rising and falling edge delays of the output buffer, providing the ability to adjust the
output-buffer duty cycle, compensate channel-to-channel skew, reduce simultaneous
switching output (SSO) noise by deliberately introducing channel-to-channel skew,
and improve high-speed memory-interface timing margins. Stratix IV devices
support four levels of output buffer delay settings. The default setting is No Delay.
For more information about programmable output buffer delay specifications, refer to
the
Stratix IV devices provide an optional open-drain output (equivalent to an open
collector output) for each I/O pin. When configured as open drain, the logic value of
the output is either high-Z or 0. Typically, an external pull-up resistor is required to
provide logic high.
Each Stratix IV device I/O pin provides an optional bus-hold feature. Bus-hold
circuitry can weakly hold the signal on an I/O pin at its last-driven state. Because the
bus-hold feature holds the last-driven state of the pin until the next input signal is
present, you do not need an external pull-up or pull-down resistor to hold a signal
level when the bus is tri-stated.
Bus-hold circuitry also pulls non-driven pins away from the input threshold voltage
where noise can cause unintended high-frequency switching. You can select this
feature individually for each I/O pin. The bus-hold output drives no higher than
V
use the programmable pull-up option. Disable the bus-hold feature if the I/O pin is
configured for differential signals.
Bus-hold circuitry uses a resistor with a nominal resistance (R
7 k Ω to weakly pull the signal level to the last-driven state.
CCIO
DC and Switching Characteristics for Stratix IV Devices
6–18, that you can activate to ensure zero hold times, minimize setup times, or
to prevent over-driving signals. If you enable the bus-hold feature, you cannot
Figure 6–17 on page
6–18. The delay chains can independently control the
chapter.
Chapter 6: I/O Features in Stratix IV Devices
chapter.
February 2011 Altera Corporation
BH
) of approximately
Figure 6–17 on
I/O Structure
DC