EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 759

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
Sharing CMU PLLs
Sharing CMU PLLs
February 2011 Altera Corporation
Calibration Clock and Power Down
Multiple Channels Sharing a CMU PLL
f
f
1
For more information about connecting these ports to the dynamic reconfiguration
controller, refer to the “Connecting the ALTGX and ALTGX_RECONFIG Instances”
section of the
Each calibration block in a Stratix IV GX and GT device is shared by multiple
transceiver blocks.
If your design uses multiple transceiver blocks, depending on the transceiver banks
selected, you must connect the cal_blk_clk and cal_blk_powerdown ports of all
channel instances to the same input pin or logic.
For more information about the calibration block and transceiver banks that are
connected to a specific calibration block, refer to the “Calibration Blocks” section in
the
Asserting the cal_blk_powerdown port affects calibration on all transceiver channels
connected to the calibration block.
When you create multiple transceiver channel instances using CMU PLLs and intend
to combine these instances in the same transceiver block, the Quartus II software
checks whether a single CMU PLL can be used to provide clock outputs for the
transmitter side of the channel instances. If a single CMU PLL is not sufficient, the
Quartus II software attempts to combine the channel instances using two CMU PLLs.
Otherwise, the Quartus II software issues a Fitter error.
The following two sections describes the ALTGX instance requirements to enable the
Quartus II software to share the CMU PLL.
To enable the Quartus II software to share the same CMU PLL for multiple channels,
the following parameters in the channel instantiations must be identical:
■
■
■
■
■
■
■
“Base data rate” (the CMU PLL is configured for this data rate)
CMU PLL bandwidth setting
Reference clock frequency
Input reference clock pin
pll_powerdown port of the ALTGX instances must be driven from the same logic
GXB_TX_PLL_Reconfig_Group assignment (refer to
If the selected functional mode in one instance is (OIF) CEI Phy Interface or PCIe,
the other instance must have the same functional mode to share the CMU PLL. For
example, if you have two channels, one configured in Basic mode and the other
configured in (OIF) CEI Phy Interface mode at the same data rate, the Quartus II
software does not share the same PLL because the internal parameters for these
two functional modes are different.
Transceiver Architecture in Stratix IV Devices
Dynamic Reconfiguration in Stratix IV Devices
chapter.
Stratix IV Device Handbook Volume 2: Transceivers
Table 3–14 on page
chapter.
3–42)
3–5