EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 776

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

3–22
Figure 3–10. Basic ×8/PCIe ×8 Functional Mode Configuration when Combining Channels (ATX PLL)
Notes to
(1) You can configure this channel in Basic (PMA Direct) single-width or double-width mode.
(2) You can configure this channel only in Basic (PMA Direct) single-width mode.
(3) The red lines represent the ×N top clock line, the blue lines represent the ×4 clock line, and the black line represents the ×N bottom clock line.
(4) To simplify the illustration, only the transmitter side is shown. PCIe ×8 refers to PCIe with the sub protocol set to Gen1 ×8 and Gen2 ×8.
Stratix IV Device Handbook Volume 2: Transceivers
Figure
3–10:
[PMA Direct] xN mode) (2)
[PMA Direct] xN mode) (2)
TX - (Basic
TX - (Basic
Master Transceiver Block
Slave Transceiver Block
CMU0 Channel
CMU0 Channel
(Basic [PMA Direct] xN mode) (1)
TX7 - Basic x8/
TX6 - Basic x8/
(PMA Direct xN mode) (1)
TX2 - Basic x8/
TX5 - Basic x8/
TX3 - Basic x8/
TX0 - Basic x8/
TX4 - Basic x8/
TX1 - Basic x8/
ATX PLL
ATX PLL
PCIe x8
PCIe x8
PCIe x8
PCIe x8
PCIe x8
PCIe x8
PCIe x8
PCIe x8
CMU1 Channel
CMU1 Channel
Central Clock
Central Clock
Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
Divider
Divider
Combining Channels Configured in Protocol Functional Modes
xN Top Clock Line (3)
x4 Clock Line (3)
x4 Clock Line (3)
xN Bottom Clock Line (3)
xN Bottom Clock Line (3)
February 2011 Altera Corporation
(Note 4)