EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 282

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

8–4
Figure 8–3. High-Speed Differential I/Os with DPA Locations in Stratix IV GT and GX Devices
LVDS Channels
Stratix IV Device Handbook Volume 1
1
Figure 8–3
The Stratix IV device family supports LVDS on both row and column I/O banks. Row
I/Os support true LVDS input with 100-Ω differential input termination (OCT R
and true LVDS output buffers. Column I/Os supports true LVDS input buffers
without OCT R
emulated LVDS output buffers that use two single-ended output buffers with an
external resistor network to support LVDS, mini-LVDS, and RSDS standards.
Stratix IV devices offer single-ended I/O refclk support for the LVDS.
Dedicated SERDES and DPA circuitries are implemented on the row I/O banks to
further enhance LVDS interface performance in the device. For column I/O banks,
SERDES is implemented in the core logic because there is no dedicated SERDES
circuitry on column I/O banks.
Emulated differential output buffers support tri-state capability starting with the
Quartus II software version 9.1.
shows a high-level chip overview of the Stratix IV GT and GX devices.
General Purpose
General Purpose
I/O and Memory
I/O and Memory
PLL
PLL
PLL
PLL
D
Interface
Interface
. Alternately, you can configure the row and column LVDS pins as
(Logic Elements, DSP,
Embedded Memory,
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Stratix IV Devices
Clock Networks)
FPGA Fabric
PLL
PLL
PLL
PLL
General Purpose
General Purpose
I/O and Memory
I/O and Memory
Interface
Interface
PLL
PLL
PLL
PLL
February 2011 Altera Corporation
LVDS Channels
D
),