EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 964

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

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Table 1–1. MegaWizard Plug-In Manager Options (General Screen for Basic Mode) (Part 3 of 10)
Stratix IV Device Handbook Volume 3
Which subprotocol will you be
using?
Enforce default settings for
this protocol.
ALTGX Setting
PCIe
In PCIe mode, there are six subprotocols:
■
■
■
■
■
■
SDI
In SDI mode, the two available subprotocols are:
■
■
SONET/SDH
In SONET/SDH mode, the three available subprotocols
and their data rates are:
■
■
■
Deterministic Latency
GIGE
(OIF) CEI PHY Interface
PCIe
SONET/SDH
XAUI
If you select this option, all mode-specific ports and
settings are used.
Gen1 ×1—The transceiver is configured as a
single-lane PCIe link for a 2.5 Gbps data rate.
Gen1 ×4—The transceiver is configured as a four-lane
PCIe link for a data rate of 2.5 Gbps.
Gen1 ×8—The transceiver is configured as an
eight-lane PCIe link for a data rate of 2.5 Gbps.
Gen2 ×1—The transceiver is configured as a
single-lane PCIe link for a 5.0 Gbps data rate.
Gen2 ×4—The transceiver is configured as a four-lane
PCIe link for a data rate of 5.0 Gbps.
Gen2 ×8—The transceiver is configured as an
eight-lane PCIe link for a data rate of 5.0 Gbps.
3G—third-generation (3 Gbps) SDI at 2967 Mbps or
2970 Mbps.
HD—high-definition SDI at 1483.5 Mbps or
1485 Mbps.
OC-12—622 Mbps
OC-48—2488.32 Mbps
OC-96—4976.64 Mbps
Description
Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
“PCIe Mode” in the
Transceiver Architecture in
Stratix IV Devices
“SDI Mode” in the
Architecture in Stratix IV
Devices
“SONET/SDH Mode” in the
Transceiver Architecture in
Stratix IV Devices
February 2011 Altera Corporation
chapter.
Reference
—
Parameter Settings
chapter.
chapter.
Transceiver