EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 924

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–78
Table 5–16. Dynamic Reconfiguration Controller Port List (ALTGX_RECONFIG Instance) (Part 3 of 13)
Stratix IV Device Handbook Volume 2: Transceivers
reconfig_fromgxb
(continued)
reconfig_togxb[3:0]
FPGA Fabric and ALTGX_RECONFIG Interface Signals
write_all
Port Name
Output
Output
Input/
Input
Input
To connect the reconfig_fromgxb port between the
ALTGX_RECONFIG instance and multiple ALTGX instances, follow
these rules:
■
■
The Quartus II Fitter produces an error if the dynamic
reconfiguration option is enabled in the ALTGX instance but the
reconfig_fromgxb and reconfig_togxb ports are not
connected to the ALTGX_RECONFIG instance.
For more information, refer to
ALTGX_RECONFIG Instances” on page
An input port of the ALTGX instance and an output port of the
ALTGX_RECONFIG instance. You must connect the
reconfig_togxb[3:0] input port of every ALTGX instance
controlled by the dynamic reconfiguration controller to the
reconfig_togxb[3:0] output port of the ALTGX_RECONFIG
instance.
The width of this port is always fixed to 3 bits.
For more information, refer to
ALTGX_RECONFIG Instances” on page
Assert this signal for one reconfig_clk clock cycle to initiate a
write transaction from the ALTGX_RECONFIG instance to the
ALTGX instance.
You can use this signal in two ways for .mif-based modes:
■
■
Connect the reconfig_fromgxb[16:0] of ALTGX Instance 1 to
the reconfig_fromgxb[16:0] of the ALTGX_RECONFIG
instance. Connect the reconfig_fromgxb[] port of the next
ALTGX instance to the next available bits of the
ALTGX_RECONFIG instance, and so on.
Connect the reconfig_fromgxb port of the ALTGX instance,
which has the highest What is the starting channel number?
option, to the MSB of the reconfig_fromgxb port of the
ALTGX_RECONFIG instance.
Continuous write operation—Select the Enable continuous
write of all the words needed for reconfiguration option to
pulse the write_all signal only once for writing a whole .mif.
The What is the read latency of the MIF contents option is
available for selection in this case only. Enter the desired latency
in terms of the reconfig_clk cycles.
Regular write operation—When the Enable continuous write of
all the words needed for reconfiguration option is disabled,
every word of the .mif requires its own write cycle.
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Description
Dynamic Reconfiguration Controller Port List
“Connecting the ALTGX and
“Connecting the ALTGX and
February 2011 Altera Corporation
5–11.
5–11.
(Note
3),
(4)