EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 95

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 4: DSP Blocks in Stratix IV Devices
Stratix IV Operational Mode Descriptions
Stratix IV Operational Mode Descriptions
February 2011 Altera Corporation
Independent Multiplier Modes
9-, 12-, and 18-Bit Multiplier
The second-stage and output registers are triggered by the positive edge of the clock
signal and are cleared after power up. The following DSP block signals control the
output registers within the DSP block:
■
■
■
This section contains an explanation of different operational modes in Stratix IV
devices.
In independent input and output multiplier mode, the DSP block performs individual
multiplication operations for general-purpose multipliers.
You can configure each DSP block multiplier for 9-, 12-, or 18-bit multiplication. A
single DSP block can support up to eight individual 9 × 9 multipliers, six individual
12 × 12 multipliers, or four individual 18 × 18 multipliers. For operand widths up to
9 bits, a 9 × 9 multiplier is implemented. For operand widths from 10 to 12 bits, a
12 × 12 multiplier is implemented, and for operand widths from 13 to 18 bits, an
18 × 18 multiplier is implemented. This is done by the Quartus II software by
zero-padding the LSBs.
the independent multiplier operation.
signals for the DSP block.
clock[3..0]
ena[3..0]
aclr[3..0]
Figure
4–8,
Figure
Table 4–9 on page 4–34
4–9, and
Figure 4–10
Stratix IV Device Handbook Volume 1
lists the dynamic
show the DSP block in
4–15