EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 719

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 2: Transceiver Clocking in Stratix IV Devices
Transceiver Channel Datapath Clocking
Table 2–12. Receiver Datapath Clock Frequencies in x4 Bonded Functional Modes without Deskew FIFO
February 2011 Altera Corporation
PCIe ×4 (Gen 1)
PCIe ×4 (Gen 2)
Functional Mode
In ×4 bonded channel configurations without deskew FIFO, the CDR in each receiver
channel recovers the serial clock from the received data. The serial recovered clock is
divided within each channel’s receiver PMA to generate the parallel recovered clock.
The deserializer uses the serial recovered clock in the receiver PMA. The parallel
recovered clock and deserialized data is forwarded to the receiver PCS in each
channel.
The parallel recovered clock from the receiver PMA in each channel clocks the word
aligner and the write side of the rate matcher FIFO in that channel. The low-speed
parallel clock from the CMU0 clock divider block in CMU0_Channel clocks the read port
of the rate match FIFO, the 8B/10B decoder, and the write port of the byte deserializer
(if enabled). The low-speed parallel clock or its divide-by-two version (if byte
deserializer is enabled) clocks the receiver phase compensation FIFO. It is also driven
on the coreclkout port as the FPGA fabric-Transceiver interface clock. You can use
the coreclkout signal to latch the receiver data and status signals in the FPGA fabric
for all four bonded channels.
Table 2–12
without deskew FIFO.
Data Rate
(Gbps)
2.5
5
lists the receiver datapath clock frequencies in ×4 bonded functional modes
Serial Recovered
Clock Frequency
(GHz)
1.25
2.5
Transmitter PCS Clock
Parallel Recovered
Clock and Parallel
Frequency (MHz)
250
500
Stratix IV Device Handbook Volume 2: Transceivers
Without Byte
Deserializer
Interface Clock Frequency
FPGA Fabric-Transceiver
(MHz)
250
N/A
Deserializer
With Byte
(MHz)
125
250
2–47