EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 476

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–32
Stratix IV Device Handbook Volume 2: Transceivers
Figure 1–28
a 20-bit wide datapath configuration.
Figure 1–28. Transmitter Bit Reversal Operation in Basic Double-Width Mode
Serializer
The serializer converts the incoming low-speed parallel signal from the transceiver
PCS to high-speed serial data and sends it to the transmitter buffer. The serializer
supports an 8-bit or 10-bit serialization factor in single-width mode and a 16-bit or
20-bit serialization factor in double-width mode. The serializer block drives the serial
data to the output buffer, as shown in
LSB of the input data.
TX bit reversal option enabled
in the ALTGX MegaWizard
shows the transmitter bit reversal feature in Basic double-width mode for
Output from transmitter PCS
D[19]
D[18]
D[17]
D[16]
D[15]
D[14]
D[13]
D[12]
D[11]
D[10]
D[9]
D[8]
D[7]
D[6]
D[5]
D[4]
D[3]
D[2]
D[1]
D[0]
Figure
Chapter 1: Transceiver Architecture in Stratix IV Devices
1–29. The serializer block sends out the
Converted data output to the
transmitter serializer
February 2011 Altera Corporation
D[10]
D[11]
D[12]
D[13]
D[14]
D[15]
D[16]
D[17]
D[18]
D[19]
D[0]
D[1]
D[2]
D[3]
D[4]
D[5]
D[6]
D[7]
D[8]
D[9]
Transceiver Block Architecture