EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 605

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–127. Receiver Input Lane Skew in XAUI Mode
February 2011 Altera Corporation
Lane 0
Lane 2
K
Lane 3
Lane 1
Receiver synchronization is indicated on the rx_syncstatus port of each channel. A
high on the rx_syncstatus port indicates that the lane is synchronized; a low on the
rx_syncstatus port indicates that it has fallen out of synchronization. The receiver
loses synchronization when it detects four invalid code groups separated by less than
four valid code groups or when it is reset.
Deskew FIFO
Code groups received across four lanes in a XAUI link can be misaligned with respect
to one another because of skew in the physical medium or differences between the
independent clock recoveries per lane. The XAUI protocol allows a maximum skew of
40 UI (12.8 ns) as seen at the receiver of the four lanes.
The XAUI protocol requires the physical layer device to implement a deskew circuitry
to align all four channels. To enable the deskew circuitry at the receiver to align the
four channels, the transmitter sends a /A/ (/K28.3/) code group simultaneously on
all four channels during inter-packet gap. The skew introduced in the physical
medium and the receiver channels can be /A/ code groups to be received misaligned
with respect to each other.
The deskew operation is performed by the deskew FIFO in XAUI functional mode.
The deskew FIFO in each channel receives data from its word aligner. The deskew
operation begins only after link synchronization is achieved on all four channels as
indicated by a high on the rx_syncstatus signal from the word aligner in each
channel. Until the first /A/ code group is received, the deskew FIFO read and write
pointers in each channel are not incremented. After the first /A/ code group is
received, the write pointer starts incrementing for each word received but the read
pointer is frozen. If the /A/ code group is received on each of the four channels
within 10 recovered clock cycles of each other, the read pointer of all four deskew
FIFOs is released simultaneously, aligning all four channels.
Figure 1–127
/A/ code group to align the channels.
Lane 0
Lane 1
Lane 2
Lane 3
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shows lane skew at the receiver input and how the deskew FIFO uses the
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Stratix IV Device Handbook Volume 2: Transceivers
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Lane Skew at
Receiver Input
Lanes are
Deskewed by
Lining up
the "Align"/A/,
Code Groups
1–161