EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 44

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

2–8
Stratix IV Device Handbook Volume 1
ALM Operating Modes
This feature, called register packing, improves device utilization because the device
can use the register and the combinational logic for unrelated functions. Another
special packing mode allows the register output to feed back into the LUT of the same
ALM so that the register is packed with its own fan-out LUT. This provides another
mechanism for improved fitting. The ALM can also drive out registered and
unregistered versions of the LUT or adder output.
The Stratix IV ALM operates in one of the following modes:
■
■
■
■
■
Each mode uses ALM resources differently. In each mode, eleven available inputs to
an ALM—the eight data inputs from the LAB local interconnect, carry-in from the
previous ALM or LAB, the shared arithmetic chain connection from the previous
ALM or LAB, and the register chain connection—are directed to different destinations
to implement the desired logic function. LAB-wide signals provide clock,
asynchronous clear, synchronous clear, synchronous load, and clock enable control
for the register. These LAB-wide signals are available in all ALM modes.
For more information about the LAB-wide control signals, refer to
Signals” on page
The Quartus II software and supported third-party synthesis tools, in conjunction
with parameterized functions such as the library of parameterized modules (LPM)
functions, automatically choose the appropriate mode for common functions such as
counters, adders, subtractors, and arithmetic functions.
Normal
Extended LUT
Arithmetic
Shared Arithmetic
LUT-Register
2–4.
Chapter 2: Logic Array Blocks and Adaptive Logic Modules in Stratix IV Devices
February 2011 Altera Corporation
“LAB Control
Adaptive Logic Modules