EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 571

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Table 1–45. PMA-PCS Interface Widths, CPRI and OSBAI Data Rates in Deterministic latency Mode
February 2011 Altera Corporation
Single-width
mode
Double-width
mode
Notes to
(1) When configured in double-width mode for the same data rate, the core clock frequency is halved.
(2) Requires double-width mode.
(3) When configured for 32/40-bit channel width requiring byte serializer/deserializer, the core clock is halved.
(4) Requires the byte serializer/deserializer.
Latency Mode
Deterministic
Table
1–45:
1
600 Mbps to
Supported
Data Rate
3.75 Gbps
> 1 Gbps
Range
Table 1–45
deterministic latency mode.
PCIe Mode
Intel Corporation has developed a PHY interface for the PCIe Architecture
specification to enable implementation of a PCIe-compliant physical layer device. The
PCIe specification also defines a standard interface between the physical layer device
and the media access control layer (MAC). Version 2.0 of the PCIe specification
provides implementation details for a PCIe-compliant physical layer device at both
Gen1 (2.5 GT/s) and Gen2 (5 GT/s) signaling rates.
To implement a Version 2.0 PCIe-compliant PHY, you must configure the
Stratix IV GX and GT transceivers in PCIe functional mode. Stratix IV GX and GT
devices have built-in PCIe hard IP blocks that you can use to implement the
PHY-MAC layer, data link layer, and transaction layer of the PCIe protocol stack. You
can also bypass the PCIe hard IP blocks and implement the PHY-MAC layer, data link
layer, and transaction layer in the FGPA fabric using a soft IP. If you enable the PCIe
hard IP blocks, the Stratix IV transceivers interface with these hard IP blocks.
Otherwise, the Stratix IV transceivers interface with the FPGA fabric.
You can configure the Stratix IV GX and GT transceivers in PCIe functional mode
using one of the following two methods:
■
■
Description of PCIe hard IP architecture and PCIe mode configurations allowed when
using the PCIe hard IP block are beyond the scope of this chapter. For more
information about the PCIe hard IP block, refer to the
ALTGX MegaWizard Plug-In Manager—if you do not use the PCIe hard IP block
PCIe Compiler—if you use the PCIe hard IP block
lists the PMA-PCS interface widths, CPRI and OSBAI data rates in
Width for CPRI
16 bit/20 bit
16 bit/20 bit
32 bit/40 bit
8 bit/10 bit
PMA-PCS
Interface
& OBSAI
CPRI Data Rate
6.144 (2), (3),
4.915 (2),
2.4576
(GBPS)
0.6144
1.2288
3.072
(4)
(1)
(3)
Frequency
PCS Clock
122.88
245.76
245.76
(MHz)
61.44
153.6
307.2
Stratix IV Device Handbook Volume 2: Transceivers
PCI Express Compiler User Guide.
6.144 (3),
OBSAI Data
3.072
(Gbps)
1.536
1.536
Rate
768
—
(3)
(4)
Frequency
PCS Clock
(MHz)
153.6
153.6
307.2
76.8
76.8
—
1–127