EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 609

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Figure 1–131. 1000 Base-X PHY in a Gigabit Ethernet OSI Reference Model
February 2011 Altera Corporation
1
Figure 1–131
model.
Stratix IV GX and GT transceivers, when configured in GIGE functional mode, have
built-in circuitry to support the following PCS and PMA functions defined in the
IEEE 802.3 specification:
■
■
■
■
■
■
Stratix IV GX and GT transceivers do not have built-in support for other PCS
functions; for example, auto-negotiation state machine, collision-detect, and
carrier-sense. If required, you must implement these functions in a PLD logic array or
external circuits.
Presentation
Model Layers
Application
Transport
Data Link
Reference
Session
Network
Physical
8B/10B encoding and decoding
Synchronization
Upstream transmitter and local receiver clock frequency compensation (rate
matching)
Clock recovery from the encoded data forwarded by the receiver PMD
Optional rx_recovclkout port enables recovered clock at the pin level (use with
VCXO)
Serialization and deserialization
OSI
shows the 1000 Base-X PHY position in a Gigabit Ethernet OSI reference
GMII
MAC (Optional)
CSMA/CD Layers
Higher Layers
Reconciliation
Medium
PCS
MAC
PMA
PMD
LLC
LAN
Stratix IV Device Handbook Volume 2: Transceivers
1000 Base-X
PHY
1–165