EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 651

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Stratix IV Devices
Built-In Self Test Modes
Figure 1–174. BIST PRBS, High Frequency, and Low Frequency Pattern Datapath
Table 1–71. Available PRBS, High Frequency, and Low Frequency Patterns in Single-Width Mode
February 2011 Altera Corporation
Patterns
PRBS 7
PRBS 8
PRBS 10
PRBS 23
High
frequency
(2)
FPGA
Fabric
PRBS in Single-Width Mode
Compen-
Polynomial
Phase
Compen-
sation
X
1010101010
FIFO
Phase
X
sation
TX
FIFO
X
X
RX
23
10
7
8
+ X
+ X
+ X
+ X
Different PRBS patterns are available as a subprotocol under Basic functional mode
for single-width and double-width mode, as shown in the following sections.
You can enable the serial loopback option in Basic PRBS mode to loop the generated
pattern to the receiver channel. This creates a rx_seriallpbken port that you can use
to dynamically control the serial loopback. The 8B/10B encoder/decoder blocks are
bypassed in Basic PRBS mode.
Figure 1–174
sent to the transmitter serializer. The verifier checks the data from the word aligner.
Table 1–71
patterns for PRBS in single-width mode configuration.
6
7
18
7
+ 1
+ 1
+ 1
+ 1
Ordering
Byte
Serializer
Byte
Width of
8 Bit
Channel
lists the various PRBS patterns and corresponding word alignment
N
Y
Y
Y
Y
serializer
shows the datapath for the PRBS patterns. The generated PRBS pattern is
Byte
De-
(1)
Encoder
8B/10B
BIST PRBS, High-Freq,
Pattern with
Width 8 Bit
Low-Freg pattern
Alignment
Receiver Channel PCS
16’h3040
16’hFF5A
Decoder
16’hFFFF
8B/10B
Channel
generator
Word
NA
NA
Width 8 Bit
Match
FIFO
Rate
Maximum
Data Rate
Channel
(Gbps)
Transmitter Channel PCS
With
N/A
2.5
2.5
2.5
2.5
BIST PRBS verifier
Deskew
FIFO
10 Bit
Width of
Stratix IV Device Handbook Volume 2: Transceivers
Channel
Aligner
Word
N
N
N
Y
Y
(1)
serializer
Receiver Channel
Serializer
Transmitter Channel PMA
De-
Alignment
PMA
Pattern
10’h3FF
Word
Receiver
NA
NA
NA
NA
CDR
can be dynamically enabled
Width 10 Bit
Serial loop back
Data Rate
Maximum
Channel
(Gbps)
3.125
3.125
with
N/A
N/A
N/A
1–207