EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 706

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

2–34
Figure 2–20. Four PCIe ×8 Links in Eight Transceiver Block Devices
Note to
(1) You can use a ×4 PCIe configuration in either a master or slave block.
Stratix IV Device Handbook Volume 2: Transceivers
PCIe Lane 3
PCIe Lane 2
PCIe Lane 1
PCIe Lane 0
PCIe Lane 3
PCIe Lane 2
PCIe Lane 1
PCIe Lane 0
PCIe Lane 7
PCIe Lane 6
PCIe Lane 5
PCIe Lane 4
PCIe Lane 7
PCIe Lane 6
PCIe Lane 5
PCIe Lane 4
Figure
2–20:
f
Figure 2–20
Non-Bonded Basic (PMA Direct) Mode Channel Configurations
Figure 2–21
configured in non-bonded Basic (PMA Direct) mode. Each channel derives its clock
independently from either the CMU0 PLL or CMU1 PLL within the same transceiver
block if the CMU channel is configured as a CMU PLL.
For more information about Basic (PMA Direct) mode, refer to the
Architecture in Stratix IV Devices
Transceiver Block
Transceiver Block
Transceiver Block
Transceiver Block
GXBL0 (Master)
EP4SGX530NF45
GXBL2 (Master)
GXBL3 (Slave)
GXBL1 (Slave)
Channel3
Channel2
Channel1
Channel0
Channel3
Channel2
Channel1
Channel0
Channel3
Channel2
Channel1
Channel0
Channel3
Channel2
Channel1
Channel0
shows four PCIe ×8 links in eight transceiver block devices.
shows four regular channels and the CMU1 channel in a transceiver block
Fourth PCIe
Third PCIe
x8 Link
x8 Link
chapter.
Second PCIe
First PCIe
x8 Link
x8 Link
(Note 1)
Chapter 2: Transceiver Clocking in Stratix IV Devices
Transceiver Block
Transceiver Block
Transceiver Block
Transceiver Block
GXBR0 (Master)
GXBR2 (Master)
GXBR3 (Slave)
GXBR1 (Slave)
Channel3
Channel2
Channel1
Channel0
Channel3
Channel2
Channel1
Channel0
Channel3
Channel2
Channel1
Channel0
Channel3
Channel2
Channel1
Channel0
Transceiver Channel Datapath Clocking
February 2011 Altera Corporation
Transceiver
PCIe Lane 7
PCIe Lane 6
PCIe Lane 5
PCIe Lane 4
PCIe Lane 7
PCIe Lane 6
PCIe Lane 5
PCIe Lane 4
PCIe Lane 3
PCIe Lane 2
PCIe Lane 1
PCIe Lane 0
PCIe Lane 3
PCIe Lane 2
PCIe Lane 1
PCIe Lane 0