EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 708

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

2–36
Stratix IV Device Handbook Volume 2: Transceivers
1
The CMU0 PLL synthesizes the input reference clock to generate a clock that is
distributed to the local clock divider block in each of the four regular channels using
the ×1 high-speed serial clock line. It is also forwarded to the CMU1 clock divider in the
CMU1 channel configured as a non-bonded Basic (PMA-Direct) channel. The local clock
divider block in each regular channel and the CMU1 clock divider in the CMU1 channel
generate the low-speed parallel clock and high-speed serial clock. The serializer in the
transmitter channel PMA of each channel uses both the low-speed parallel clock and
high-speed serial clock for its parallel-in-serial-out operation.
The low-speed parallel clock is also driven directly on the tx_clkout port as the FPGA
fabric-Transceiver interface clock. You can use the tx_clkout port to clock transmitter
data and control logic in the FPGA fabric.
Bonded Basic (PMA Direct) ×N Mode Channel Configurations
Bonded Basic (PMA Direct) ×N mode offers low transmitter channel-to-channel skew
in addition to the flexibility of implementing custom PCS logic in the FPGA fabric.
Stratix IV devices allow bonding all regular channels and CMU channels on one side
of the device in Basic (PMA Direct) ×N mode. For example, devices such as
EP4SGX530NF45 or EP4S100G5F45 allow bonding of up to 24 channels placed in four
transceiver blocks on each side of the device.
The coreclkout port is not available in Basic (PMA Direct) ×N mode.
In bonded channel configurations, the CMU0 clock divider of all the transceiver blocks
is used, as shown in
(PMA Direct) ×N configuration:
■
■
If you use the ATX PLL to generate the transceiver datapath interface clocks, only
the clock divider of the ATX PLL is used.
If you use the CMU PLL to generate the transceiver datapath interface clocks, only
the CMU0 clock divider block of the transceiver block containing the CMU PLL is
used.
Figure
2–17. Unlike bonded channel configurations, in Basic
Chapter 2: Transceiver Clocking in Stratix IV Devices
Transceiver Channel Datapath Clocking
February 2011 Altera Corporation