EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 484
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP4SGX110DF29C3N PDF datasheet
- EP4SGX110DF29C3N PDF datasheet #2
- EP4SGX110DF29C3N PDF datasheet #3
- EP4SGX110DF29C3N PDF datasheet #4
- EP4SGX110DF29C3N PDF datasheet #5
- EP4SGX110DF29C3N PDF datasheet #6
- EP4SGX530HH35C2N PDF datasheet #7
- Current page: 484 of 1154
- Download datasheet (32Mb)
1–40
Stratix IV Device Handbook Volume 2: Transceivers
Receiver Channel Datapath
This section describes the Stratix IV GX and GT receiver channel datapath
architecture. The sub-blocks in the receiver datapath are described in order from the
serial receiver input buffer to the receiver phase compensation FIFO buffer at the
FPGA fabric-transceiver interface.
channel datapath in Stratix IV GX and GT devices.
The receiver channel PMA datapath consists of the following blocks:
■
■
■
The receiver channel PCS datapath consists of the following blocks:
■
■
■
■
■
■
■
■
The receiver datapath is very flexible and allows multiple configurations, depending
on the selected functional mode. You can configure the receiver datapath using the
ALTGX MegaWizard Plug-In Manager.
Receiver Input Buffer
The Stratix IV GX and GT receiver input buffers are architecturally similar to each
other. They both support programmable common mode voltage (Rx VCM),
equalization, DC gain, and on-chip termination (OCT) settings.
supported settings of the receiver input buffers in Stratix IV GX and GT devices.
The receiver input buffer receives serial data from the rx_datain port and feeds it to
the CDR unit. In the reverse serial loopback (pre-CDR) configuration, it also feeds the
received serial data to the transmitter output buffer.
input buffer.
Receiver input buffer
Clock and data recovery (CDR) unit
Deserializer
Word aligner
Deskew FIFO
Rate match (clock rate compensation) FIFO
8B/10B decoder
Byte deserializer
Byte ordering
Receiver phase compensation FIFO
PCIe interface
Figure 1–12 on page 1–17
Chapter 1: Transceiver Architecture in Stratix IV Devices
Figure 1–36
shows the receiver
February 2011 Altera Corporation
Table 1–17
Transceiver Block Architecture
shows the receiver
lists the
Related parts for EP4SGX530HH35C2N
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
CYCLONE II STARTER KIT EP2C20N
Manufacturer:
Altera
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 35 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 15 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 30 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 7ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Classic EPLD
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
High-performance, low-power erasable programmable logic devices with 8 macrocells, 10ns
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
Manufacturer:
Altera Corporation
Datasheet:
Part Number:
Description:
CPLD, EP610 Family, ECMOS Process, 300 Gates, 16 Macro Cells, 16 Reg., 16 User I/Os, 5V Supply, 25 Speed Grade, 24DIP
Manufacturer:
Altera Corporation
Datasheet: