EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 642

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–198
Figure 1–163. Location of Transceiver Channel and PLL in Stratix IV GT Devices (EP4S40G2F40, EP4S40G5H40,
EP4S100G2F40 and EP4S100G5H40)
Figure 1–164. Location of Transceiver Channel and PLL in Stratix IV GT Devices (EP4S100G5F45)
Stratix IV Device Handbook Volume 2: Transceivers
Input Reference Clocks for the ATX PLL Block
Figure 1–163
each Stratix IV GT device.
The 6G ATX PLL block does not have a dedicated reference clock pin. The following
are the possible input reference clock sources:
■
■
■
Altera recommends using the REFCLK pins from the adjacent transceiver block below
the ATX PLL block to improve performance.
REFCLKs from the transceiver blocks on the same side of the device if the
corresponding CMU channels are not used as transceiver channels
Input reference clock provided through the PLL cascade clock network
Clock inputs connected through the global clock lines
Transceiver Block GXBL2
Transceiver Block GXBL1
Transceiver Block GXBL0
Transceiver Block GXBL2
Transceiver Block GXBL3
Transceiver Block GXBL1
Transceiver Block GXBL0
ATX PLL L1 (10G)
ATX PLL L0 (6G)
ATX PLL L2 (10G)
ATX PLL L1 (6G)
ATX PLL L0 (6G)
and
Figure 1–164
show the locations of the 6G and 10G ATX PLLs in
Transceiver Block GXBR2
Transceiver Block GXBR0
Transceiver Block GXBR3
Transceiver Block GXBR2
Transceiver Block GXBR1
Transceiver Block GXBR0
Transceiver Block GXBR1
Chapter 1: Transceiver Architecture in Stratix IV Devices
ATX PLL R2 (10G)
ATX PLL R1 (6G)
ATX PLL R0 (6G)
ATX PLL R1 (10G)
ATX PLL R0 (6G)
Auxiliary Transmit (ATX) PLL Block
February 2011 Altera Corporation