EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 702

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

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Stratix IV Device Handbook Volume 2: Transceivers
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The eight bonded channels are located in two transceiver blocks, referred to as the
master transceiver block and the slave transceiver block, with four channels each.
When clocked using a CMU PLL, the CMU0 clock divider in CMU0 channel of the master
transceiver block drives the high-speed serial clock and low-speed parallel clock on
the xN_Top clock line. The serializer in the transmitter channel PMA of all eight
bonded channels uses the same low-speed parallel clock and high-speed serial clock
driven by the CMU0 channel of the master transceiver block on the xN_Top clock line.
The low-speed parallel clock from CMU0 channel of the master transceiver block clocks
the 8B/10B encoder and the write port of the byte serializer (if enabled) in the
transmitter channel PCS of all eight channels.
Depending on whether you use the byte serializer or not, the low-speed parallel clock
(when you do not use the byte serializer) or a divide-by-two version of the low-speed
parallel clock (when you use the byte serializer) from the CMU0 clock divider block
clocks the read port of the transmitter phase compensation FIFO in all eight bonded
channels. This clock is driven directly on the coreclkout port as the FPGA
fabric-Transceiver interface clock. You can use the coreclkout signal to clock the
transmitter data and control logic in the FPGA fabric for all eight bonded channels.
If you choose the ATX PLL to generate the transceiver clocks for the ×8 bonded
channels, Altera recommends placing the ATX PLL between the master and slave
transceiver block to minimize transmitter channel-to-channel skew. In this
configuration, the ATX PLL block drives the high-speed serial clock and low-speed
parallel clock to the master transceiver block on the ×N_Bottom lines. It drives the
high-speed serial clock and low-speed parallel clock to the slave transceiver block on
the ×N_Top lines.
For more information, refer to the
Stratix IV Devices
In PCIe ×8 and Basic ×8 bonded channel configurations, the transmitter phase
compensation FIFOs in all eight bonded channels share common read and write
pointers and enable signals generated in the CCU of the master transceiver block. This
ensures equal transmitter phase compensation FIFO latency across all eight bonded
channels, resulting in low transmitter channel-to-channel skew.
The difference in clock routing delays between the ×4 clock lines and the ×N clock
lines can result in higher transmitter channel-to-channel skew. To compensate for this
difference in clock routing delays between the ×4 and the ×N clock lines, the Stratix IV
transceivers introduce a fixed amount of delay in the ×4 clock lines of the transceiver
block whose CMU0 channel generates the transceiver clocks in Basic ×8 bonded channel
configuration.
chapter.
Configuring Multiple Protocols and Data Rates in
Chapter 2: Transceiver Clocking in Stratix IV Devices
Transceiver Channel Datapath Clocking
February 2011 Altera Corporation