EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 154

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

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Stratix IV Device Handbook Volume 1
Spread-Spectrum Tracking
Clock Switchover
Stratix IV devices can accept a spread-spectrum input with typical modulation
frequencies. However, the device cannot automatically detect that the input is a
spread-spectrum signal. Instead, the input signal looks like deterministic jitter at the
input of the PLL. Stratix IV PLLs can track a spread-spectrum input clock as long as it
is within input-jitter tolerance specifications. Stratix IV devices cannot internally
generate spread-spectrum clocks.
The clock switchover feature allows the PLL to switch between two reference input
clocks. Use this feature for clock redundancy or for a dual-clock domain application
such as in a system that turns on the redundant clock if the previous clock stops
running. The design can perform clock switchover automatically when the clock is no
longer toggling or based on a user control signal, clkswitch.
The following clock switchover modes are supported in Stratix IV PLLs:
■
■
■
Automatic switchover—The clock sense circuit monitors the current reference
clock and if it stops toggling, automatically switches to the other inclk0 or inclk1
clock.
Manual clock switchover—Clock switchover is controlled using the clkswitch
signal. When the clkswitch signal goes from logic low to logic high, and stays
high for at least three clock cycles, the reference clock to the PLL is switched from
inclk0 to inclk1, or vice-versa.
Automatic switchover with manual override—This mode combines automatic
switchover and manual clock switchover. When the clkswitch signal goes high, it
overrides the automatic clock switchover function. As long as the clkswitch signal
is high, further switchover action is blocked.
Chapter 5: Clock Networks and PLLs in Stratix IV Devices
February 2011 Altera Corporation
PLLs in Stratix IV Devices