EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 963

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: ALTGX Transceiver Setup Guide for Stratix IV Devices
Parameter Settings
Table 1–1. MegaWizard Plug-In Manager Options (General Screen for Basic Mode) (Part 2 of 10)
February 2011 Altera Corporation
Which subprotocol will you be
using?
ALTGX Setting
Basic
In Basic mode, the subprotocols are diagnostic modes.
The available options are as follows:
■
■
■
■
■
Basic (PMA Direct)
■
■
Deterministic Latency
■
■
None—This is the normal operation of the transceiver.
×4—In this mode, all four channels within the
transceiver block are clocked from its central clock
divider block to minimize transmitter
channel-to-channel skew.
×8—In this mode, all eight channels in two
transceiver blocks are clocked from the central clock
divider of the master transceiver block to minimize
transmitter channel-to-channel skew.
BIST—This subprotocol is applicable only for
Receiver and Transmitter operation mode. This mode
loops the parallel data from the built-in self test (BIST)
(non-PRBS) back to the BIST verifier in the receiver
path. Parallel loopback is allowed only in Basic
double-width mode.
PRBS—This subprotocol is applicable only for
Receiver and Transmitter operation mode.This is
another Serial Loopback mode but with the
pseudo-random binary sequence (PRBS) BIST block
active. The PRBS pattern depends on the
serializer/deserializer (SERDES) factor.
None—This is the normal mode of operation in which
each channel is treated independently.
XN—In this mode, the “N” in XN represents the
number of channels in the bonded configuration. All
N channels are clocked by the same transmit clock
from the central clock divider block to minimize
transmitter channel-to-channel skew.
×1—In this mode, you can have up to two configured
channels per transceiver block. Each channel uses one
CMU PLL and its feedback path to compensate for the
uncertain latency.
×4—In this mode, you can have up to four configured
channels per transceiver block. All channels use one
CMU PLL per block and its feedback path to
compensate for the uncertain latency.
Description
“Basic Functional Mode”
section in the
Architecture in Stratix IV
Devices
“Basic PMA Direct Functional
Mode” section in the
Transceiver Architecture in
Stratix IV Devices
“Deterministic Latency Mode”
section in the
Architecture in Stratix IV
Devices
Stratix IV Device Handbook Volume 3
chapter.
chapter.
Reference
Transceiver
Transceiver
chapter.
1–5