EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 860

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–14
Figure 5–5. Method 1—Write Transaction Waveform
Stratix IV Device Handbook Volume 2: Transceivers
logical_address_channel [1:0]
rx_tx_duplex_sel [1:0]
Figure 5–5
example, the number of channels connected to the dynamic reconfiguration controller
is four. Therefore, the logical_channel_address port is 2 bits wide. Also, to initiate
the write transaction, you must assert the write_all signal for one reconfig_clk
cycle.
tx_vodctrl [2:0]
reconfig_clk
Write Transaction
write_all
busy
shows the write transaction waveform when using Method 1. In this
2’b00
2’b00
3’b00
2’b01 (second channel of the ALTGX instance)
2’b10 (transmitter portion only)
3’b11
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
February 2011 Altera Corporation