EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 263

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 7: External Memory Interfaces in Stratix IV Devices
Stratix IV External Memory Interface Features
February 2011 Altera Corporation
f
1
You can use either a static phase offset or a dynamic phase offset to implement the
additional phase shift. The available additional phase shift is implemented in 2’s:
complement in Gray-code between settings –64 to +63 for frequency mode 0, 1, 2, and
3, and between settings –32 to +31 for frequency modes 4, 5, 6, and 7. An additional bit
indicates whether the setting has a positive or negative value. The settings are linear,
each phase offset setting adds a delay amount specified in the
Characteristics for Stratix IV Devices
delay settings and the user-selected phase offset settings whose top setting is 64 for
frequency modes 0, 1, 2, and 3; and 32 for frequency modes 4, 5, 6, and 7, so the actual
physical offset setting range is 64 or 32 subtracted by the DQS delay settings from the
DLL.
When using this feature, you need to monitor the DQS delay settings to know how
many offsets you can add and subtract in the system. Note that the DQS delay settings
output by the DLL are also Gray coded.
For example, if the DLL determines that DQS delay settings of 28 is needed to achieve
a 30° phase shift in DLL frequency mode 1, you can subtract up to 28 phase offset
settings and you can add up to 35 phase offset settings to achieve the optimal delay
that you need. However, if the same DQS delay settings of 28 is needed to achieve 30°
phase shift in DLL frequency mode 4, you can still subtract up to 28 phase offset
settings, but you can only add up to 3 phase offset settings before the DQS delay
settings reach their maximum settings because DLL frequency mode 4 only uses 5-bit
DLL delay settings.
For more information about the value for each step, refer to the
Characteristics for Stratix IV Devices
When using static phase offset, you can specify the phase offset amount in the
ALTMEMPHY megafunction as a positive number for addition or a negative number
for subtraction. You can also have a dynamic phase offset that is always added to,
subtracted from, or both added to and subtracted from the DLL phase shift. When
you always add or subtract, you can dynamically input the phase offset amount into
the dll_offset[5..0] port. When you want to both add and subtract dynamically,
you control the addnsub signal in addition to the dll_offset[5..0] signals.
chapter. The DQS phase shift is the sum of the DLL
chapter.
Stratix IV Device Handbook Volume 1
DC and Switching
DC and Switching
7–43