EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 796

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

3–42
Combination Requirements When You Enable Channel Reconfiguration
Stratix IV Device Handbook Volume 2: Transceivers
Combination Requirements When You Enable the Use Alternate CMU PLL
Option
f
1
You can configure a transmitter channel to:
■
■
For more information about setting up the transceiver to enable one of these three
options, refer to the
The section describes the combination requirements for an instance that is configured
in one of the three options mentioned above with other instances.
If you create a transceiver instance by selecting the use alternate CMU PLL option,
the Quartus II software uses two CMU PLLs. If you intend to combine other
transmitter instances within the same transceiver block, the CMU PLLs must be
shared between multiple instances. To enable the Quartus II software to share the
CMU PLLs between these instances, you must:
1. Select the user alternate CMU PLL option in all the instances.
2. Set the same PLL logical reference index value for the similar PLLs between the
3. Create a GXB TX PLL Reconfiguration group setting in the assignment editor and
Table 3–14
Table 3–14. Assignment for the First Instance—Instance 1
Table 3–15
Table 3–15. Assignment for the Second Instance—Instance 2
Ensure that the requirements specified in the
Channels” on page 3–3
To
Assignment Name
Value
To
Assignment Name
Value
Switch to an alternate CMU PLL present within the same transceiver block.
Switch to multiple TX PLLs (CMU or ATX PLLs) that are present outside the
transceiver block.
two instances (similar PLLs are the ones that have the same data rate, input clock
frequency, and bandwidth setting).
assign the same value for both instances. This setting is required for all instances
and channels controlled by the shared ALT_GX_Reconfig.
Assignment
Assignment
lists the assignment for the first instance (Instance 1).
lists the assignment for the second instance (Instance 2).
Dynamic Reconfiguration in Stratix IV Devices
<provide the tx_dataout port name of first instance>
GXB TX PLL Reconfiguration group setting
<any number>
<provide the tx_dataout port name of second instance>
GXB TX PLL Reconfiguration group setting
<same number as that of the first instance>
and
Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
“Sharing CMU PLLs” on page 3–5
Combination Requirements When You Enable Channel Reconfiguration
“General Requirements to Combine
Setting
Setting
February 2011 Altera Corporation
sections are met.
chapter.