EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 845

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 4: Reset Control and Power Down in Stratix IV Devices
Simulation Requirements
Simulation Requirements
Reference Information
February 2011 Altera Corporation
The following are simulation requirements:
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■
■
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For more information about some useful reference terms used in this chapter, refer to
the links listed in
Table 4–9. Reference Information (Part 1 of 2)
Dynamic Reconfiguration Reset Sequences
The gxb_powerdown port is optional. In simulation, if the gxb_powerdown port is not
instantiated, you must assert the tx_digitalreset, rx_digitalreset, and
rx_analogreset signals appropriately for correct simulation behavior.
If the gxb_powerdown port is instantiated, and the other reset signals are not used,
you must assert the gxb_powerdown signal for at least one parallel clock cycle for
correct simulation behavior.
You can de-assert the rx_digitalreset signal immediately after the
rx_freqlocked signal goes high to reduce the simulation run time. It is not
necessary to wait for t
The busy signal is de-asserted after about 20 parallel reconfig_clk clock cycles in
order to reduce simulation run time. For silicon behavior in hardware, you can
follow the reset sequences described in the previous pages.
In PCIe mode simulation, you must assert the tx_forceelecidle signal for at least
one parallel clock cycle before transmitting normal data for correct simulation
behavior.
Non-Bonded channel configuration
Basic (PMA Direct) Drive xN Mode
Basic (PMA Direct) Drive x1 Mode
Bonded channel configuration
Terms Used in this Chapter
Automatic Lock Mode
rx_digitalreset
Manual Lock Mode
rx_analogreset
gxb_powerdown
pll_powerdown
rx_freqlocked
pll_locked
Table
busy
PCIe
LTD
LTR
4–9.
LTD_Auto
(as suggested in the actual reset sequence).
Stratix IV Device Handbook Volume 2: Transceivers
Useful Reference Points
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