EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 157

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 5: Clock Networks and PLLs in Stratix IV Devices
PLLs in Stratix IV Devices
February 2011 Altera Corporation
Figure 5–36
both clock sources are functional and inclk0 is selected as the reference clock;
clkswitch goes high, which starts the switchover sequence. On the falling edge of
inclk0, the counter’s reference clock, muxout, is gated off to prevent clock glitching.
On the falling edge of inclk1, the reference clock multiplexer switches from inclk0 to
inclk1 as the PLL reference and the activeclock signal changes to indicate which
clock is currently feeding the PLL.
Figure 5–36. Clock Switchover Using the clkswitch (Manual) Control
Note to
(1) To initiate a manual clock switchover event, both inclk0 and inclk1 must be running when the clkswitch signal
In automatic override with manual switchover mode, the activeclock signal mirrors
the clkswitch signal. As both clocks are still functional during the manual switch,
neither clkbad signal goes high. Because the switchover circuit is positive-edge
sensitive, the falling edge of the clkswitch signal does not cause the circuit to switch
back from inclk1 to inclk0. When the clkswitch signal goes high again, the process
repeats. clkswitch and automatic switch only work if the clock being switched to is
available. If the clock is not available, the state machine waits until the clock is
available.
goes high.
Figure
5–36:
shows a clock switchover waveform controlled by clkswitch. In this case,
activeclock
clkswitch
clkbad0
clkbad1
muxout
inclk0
inclk1
Stratix IV Device Handbook Volume 1
(Note 1)
5–41