EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 628

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–184
Table 1–67. Synchronization State Machine Parameters in Serial RapidIO Mode
Stratix IV Device Handbook Volume 2: Transceivers
Number of valid K28.5 code groups received to achieve synchronization.
Number of errors received to lose synchronization.
Number of continuous good code groups received to reduce the error count by one.
Synchronization State Machine
In Serial RapidIO mode, the ALTGX MegaWizard Plug-In Manager defaults the word
alignment pattern to K28.5. The word aligner has a synchronization state machine that
handles the receiver lane synchronization.
The ALTGX MegaWizard Plug-In Manager automatically defaults the
synchronization state machine to indicate synchronization when the receiver receives
127 K28.5 (10'b0101111100 or 10'b1010000011) synchronization code groups without
receiving an intermediate invalid code group. After synchronization, the state
machine indicates loss of synchronization when it detects three invalid code groups
separated by less than 255 valid code groups or when it is reset.
Receiver synchronization is indicated on the rx_syncstatus port of each channel. A
high on the rx_syncstatus port indicates that the lane is synchronized and a low
indicates that it has fallen out of synchronization.
Table 1–67
when configured in Serial RapidIO mode.
lists the ALTGX megafunction synchronization state machine parameters
Parameters
Chapter 1: Transceiver Architecture in Stratix IV Devices
February 2011 Altera Corporation
Transceiver Block Architecture
Number
127
255
3