EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 252

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

7–32
Figure 7–22. Stratix IV DLL and I/O Bank Locations (Die-Top View)
Stratix IV Device Handbook Volume 1
PLL_L2
PLL_L3
1C
PLL_L4
PLL_L1
1A
1B
2C
2A
2B
DLL0
DLL1
6
6
Figure 7–22
die-top view if all sides of the device support external memory interfaces.
The DLL can access the two adjacent sides from its location within the device. For
example, DLL0 on the top left of the device can access the top side (I/O banks 7A, 7B,
7C, 8A, 8B, and 8C) and the left side of the device (I/O banks 1A, 1B, 1C, 2A, 2B, and
2C). This means that each I/O bank is accessible by two DLLs, giving more flexibility
to create multiple frequencies and multiple-type interfaces. You can have two
different interfaces with the same frequency on the two sides adjacent to a DLL, where
the DLL controls the DQS delay settings for both interfaces.
Each bank can use settings from either or both DLLs the bank is adjacent to. For
example, DQS1L can get its phase-shift settings from DLL0, while DQS2L can get its
phase-shift settings from DLL1.
banks for Stratix IV devices.
6
6
8A
3A
shows the DLL and I/O bank locations in Stratix IV devices from a
8B
3B
3C
8C
PLL_T1
PLL_B1
Stratix IV FPGA
Table 7–4
PLL_T2
PLL_B2
Chapter 7: External Memory Interfaces in Stratix IV Devices
lists the DLL location and supported I/O
7C
4C
4B
7B
Stratix IV External Memory Interface Features
4A
7A
6
February 2011 Altera Corporation
6
DLL3
DLL2
6
6
PLL_R4
PLL_R1
PLL_R2
PLL_R3
6C
6A
6B
5C
5B
5A