EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 868

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

5–22
Stratix IV Device Handbook Volume 2: Transceivers
1
1
1
A .mif is generated for every ALTGX instance defined in the top-level RTL file.
The Quartus II software creates the .mif under the <Project_DIR>/reconfig_mif folder.
The file name is based on the ALTGX instance name (<instance name>.mif); for
example, basic_gxb.mif. One design can have multiple .mifs (there is no limit) and
you can use one .mif to reconfigure multiple channels.
To generate a .mif, create a top-level design and connect the clock inputs in the
RTL/schematic. Specifically, for the transceiver clock inputs pll_inclk_cruclk.
If you do not specify pins for tx_dataout and rx_datain for the transceiver channel,
the Quartus II software selects a channel and generates a .mif for that channel.
However, the .mif can still be used for any transceiver channel.
You can generate multiple .mifs in the following two ways:
Method 1:
1. Compile the design created and generate the first .mif.
2. Update the ALTGX instance with the alternate configuration.
3. Compile the design to get the second .mif.
If you have to generate .mifs for many configurations, Method 1 takes more time to
complete.
Method 2:
1. In the top-level design, instantiate all the different configurations of the ALTGX
2. Connect the appropriate clock inputs of all the ALTGX instantiations.
3. Generate the .mif. The .mifs are generated for all the ALTGX configurations.
This method requires special attention when generating the .mif. Refer to the
following:
.mif-Based Design Flow
The .mif-based design flow involves writing the contents of the .mif to the transceiver
channel or CMU PLL.
instantiation for which the .mif is required.
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■
■
The different ALTGX instantiations must have the appropriate logical
reference clock index option values.
The clock inputs for each instance must be connected to the appropriate clock
source.
When you generate the .mif, use the proper naming convention for the files so
you know the configuration supported by the .mif.
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
February 2011 Altera Corporation