EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 568

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–124
Figure 1–103. CPRI Topologies
Stratix IV Device Handbook Volume 2: Transceivers
1
In order to achieve deterministic latency through the transceiver, the reference clock
to the CMU PLL must be the same as the low-speed parallel clock. For example, if you
need a data rate of 1.2288 Gbps to be implemented for the CPRI protocol that places
stringent requirements on the amount of latency variation, you must choose a
reference clock of 122.88 MHz to allow for a feedback path from the CMU PLL to be
used. This feedback path reduces the variations in latency.
When selecting this option, you must provide an input reference clock to the CMU
PLL that is of the same frequency as the low-speed parallel clock.
In a CPRI implementation, the input reference clock to the CMU PLL must be the
same as the low-speed parallel clock. Each CPRI channel uses one CMU PLL;
therefore, each transceiver block can implement two CPRI ×1 channels only.
ATX PLLs do not have the feedback path enabled; therefore, they cannot be used for
implementing the CPRI configuration.
In the deterministic latency ×4 option, up to four CPRI TX channels can be bundled in
an ×4 group so that they all have the same TX uncertainty and just require one TX PLL
to compensate for it. This is allowed in cases where the data rates are multiples of a
single PLL output frequency; for example, 0.6144 Gbps, 1.228 Gbps, 2.4576 Gbps, and
4.9152 Gbps. For ×4 bundled channels to maintain PLL lock during auto-negotiation,
the IP must use over-sampling (sending the same bit multiple times) to output lower
auto-negotiated line rates. Do not use the hard 8B/10B for oversampled channels.
CPRI and OBSAI
You can use deterministic latency functional mode to implement protocols such as
CPRI and OBSAI.
The CPRI interface defines a digital point-to-point interface between the Radio
Equipment Control (REC) and the Radio Equipment (RE) allowing flexibility in either
co-locating the REC and the RE or remote location of the RE.
various CPRI topologies. In most cases, CPRI links are between REC and RE modules
or between two RE modules in a chain configuration.
RE
RE
RE
RE
Ring
Chain
RE
RE
Radio Equipment
Control
REC
Piont-to-Point
Chapter 1: Transceiver Architecture in Stratix IV Devices
RE
RE
Tree and Branch
RE
RE
February 2011 Altera Corporation
Figure 1–103
Transceiver Block Architecture
shows