EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 760
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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3–6
Stratix IV Device Handbook Volume 2: Transceivers
Each channel instance can have a different local divider setting. This is a useful option
when you intend to run each channel within the transceiver block at different data
rates that are derived from the same base data rate using the local divider values /1,
/2, and /4.
Example 1
Consider an example design with four instances of a Receiver and Transmitter
configuration in the same transceiver block at various serial data rates. Assume that
each instance contains a channel and is driven from the same clock source and has the
same CMU PLL bandwidth settings.
Table 3–2. Configuration for Example 1
For Example 1, you can share a single CMU PLL for all four channels because:
■
■
To enable the Quartus II software to share a single CMU PLL for all four channels, set
the values listed in
Plug-In Manager.
Table 3–3. ALTGX MegaWizard Plug-In Manager Settings for Example 1
One CMU PLL can be configured to run at 4.25 Gbps.
Each channel can divide the CMU PLL clock output using the local divider and
achieve the required data rates of 4.25 Gbps, 2.125 Gbps, and 1.0625 Gbps. Because
each receiver channel has a dedicated CDR, the receiver side in each instance can
be set up for these three data rates without any restrictions.
Instance Name
User-Created
Instance
inst0
inst1
inst2
inst3
inst0
inst1
inst2
Example 1
Table 3–3
shows this design configuration.
Number of Channels
What is the effective data rate?
Specify base data rate
What is the effective data rate?
Specify base data rate
What is the effective data rate?
Specify base data rate
Chapter 3: Configuring Multiple Protocols and Data Rates in Stratix IV Devices
in the General screen of the ALTGX MegaWizard
1
1
1
1
General Screen Option
ALTGX MegaWizard Plug-In Manager Settings
Table 3–2
lists the configuration for Example 1.
Configuration
Receiver and
Receiver and
Receiver and
Receiver and
Transmitter
Transmitter
Transmitter
Transmitter
February 2011 Altera Corporation
Effective Data Rate
Setting (Gbps)
4.25
4.25
4.25
1.0625
(Gbps)
1.0625
Sharing CMU PLLs
2.125
2.125
4.25
4.25
4.25
(1)
(1)
(1)
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