EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 598

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–154
Figure 1–122. Example of Mapping XGMII Characters to PCS Code Groups
Stratix IV Device Handbook Volume 2: Transceivers
T/RxD<23..16>
T/RxD<31..24>
T/RxD<15..8>
T/RxD<7..0>
Lane 0
Lane 1
Lane 2
Lane 3
The XGMII interface consists of four lanes of 8 bits. At the transmit side of the XAUI
interface, the data and control characters are converted within the XGXS into an
8B/10B encoded data stream. Each data stream is then transmitted across a single
differential pair running at 3.125 Gbps (3.75 Gbps for HiGig). At the XAUI receiver,
the incoming data is decoded and mapped back to the 32-bit XGMII format. This
provides a transparent extension of the physical reach of the XGMII and also reduces
the interface pin count.
In Stratix IV GX and GT XAUI functional mode, the interface between the transceiver
and FPGA fabric is 64 bits wide (four channels of 16 bits each) at single data rate.
XAUI functions as a self-managed interface because code group synchronization,
channel deskew, and clock domain decoupling is handled with no upper layer
support requirements. This functionality is based on the PCS code groups that are
used during the IPG time and idle periods. PCS code groups are mapped by the XGXS
to XGMII characters, as listed in
Table 1–58. XGMII Character to PCS Code-Group Mapping
Figure 1–122
code groups that are used in XAUI. The idle characters are mapped to a
pseudo-random sequence of /A/, /R/, and /K/ code groups.
Note to
(1) The values in the XGMII TXD column are in hexadecimal.
XGMII TXC
XGMII
PCS
K
K
K
K
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Table
0
1
1
1
1
1
1
1
R
R
R
R
|
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1–58:
Dp
Dp
Dp
Dp
Dp
Dp
shows an example of mapping between XGMII characters and the PCS
S
S
Dp
Dp
Dp
Dp
Dp
Dp
Dp
Dp
Any other value
XGMII TXD
00 through FF
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
9C
FD
07
07
FB
FE
D
D
D
D
D
D
D
D
(1)
Table
- - -
- - -
- - -
- - -
- - -
- - -
- - -
- - -
D
D
D
D
D
D
D
D
K28.0 or K28.3 or K28.5
1–58.
D
D
D
D
D
D
D
D
PCD Code Group
Chapter 1: Transceiver Architecture in Stratix IV Devices
D
D
D
D
D
D
D
D
K28.5
K28.4
K27.7
K29.7
K30.7
K30.7
Dxx,y
D
T
D
T
K
K
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A
A
A
A
|
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R
R
R
R
|
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February 2011 Altera Corporation
R
R
R
R
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Normal data transmission
Invalid XGMII character
Transceiver Block Architecture
K
K
K
K
|
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K
K
K
K
Description
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Idle in ||T||
Idle in ||I||
Sequence
Terminate
Error
Start
R
R
R
R
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