EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 450

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–6
Stratix IV Device Handbook Volume 2: Transceivers
Figure 1–3
Stratix IV GX device that has 24 or 36 transceiver channels (except for the EP4SGX530
device).
Figure 1–3. Transceiver Channel, PLL, and PCIe Hard IP Block Locations with 24 or 36
Stratix IV GX Transceiver Channels (Except the EP4SGX530 Device)
Note to
(1) The 6G ATX PLL R1 and L1 blocks are not available in the EP4SGX230KF40 devices.
Figure
shows transceiver channel, PLL, and PCIe hard IP block locations in each
1–3:
EP4SGX180KF40, EP4SGX230KF40 (1), EP4SGX290KF40, EP4SGX290KF43,
EP4SGX360KF43, EP4SGX360KF40,
Transceiver Block GXBL2
Transceiver Block GXBL0
Transceiver Block GXBL1
ATX PLL L1 (6G) (1)
EP4SGX180HF35, EP4SGX230HF35, EP4SGX290HF35,
EP4SGX360HF35,
CMU Channel 1
CMU Channel 0
CMU Channel 1
CMU Channel 0
ATX PLL L0 (6G)
CMU Channel 1
CMU Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 1
Channel 0
Channel 3
Channel 2
(24 transceivers)
(36 transceivers)
Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block GXBR1
Transceiver Block GXBR0
Transceiver Block GXBR2
ATX PLL R1 (6G) (1)
CMU Channel 1
CMU Channel 0
ATX PLL R01 (6G)
CMU Channel 1
CMU Channel 0
CMU Channel 1
CMU Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 3
Channel 2
Channel 1
Channel 0
Channel 1
Channel 0
Channel 3
Channel 2
February 2011 Altera Corporation
Transceiver Channel Locations