EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 676

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

2–4
Figure 2–2. Input Reference Clock Sources in a Transceiver Block
Stratix IV Device Handbook Volume 2: Transceivers
refclk1
refclk0
Figure 2–2
within a transceiver block. One global clock line is available for each CMU PLL and
receiver CDR in a transceiver block. This allows each CMU PLL and receiver CDR to
derive its input reference clock from a separate FPGA CLK input pin.
2
2
shows the input reference clock sources for CMU PLLs and receiver CDRs
PLL Cascade Clock
PLL Cascade Clock
PLL Cascade Clock
PLL Cascade Clock
PLL Cascade Clock
PLL Cascade Clock
Global Clock Line
Global Clock Line
Global Clock Line
Global Clock Line
Global Clock Line
Global Clock Line
ITB Clock Lines
ITB Clock Lines
ITB Clock Lines
ITB Clock Lines
ITB Clock Lines
ITB Clock Lines
6
6
6
6
6
6
Chapter 2: Transceiver Clocking in Stratix IV Devices
CMU1 PLL
CDR
CDR
CMU0 PLL
CDR
CDR
Transceiver Block
February 2011 Altera Corporation
CMU1 Channel
CMU0 Channel
Channel 3
Channel 2
Channel 1
Channel 0
Input Reference Clocking