EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 880
EP4SGX530HH35C2N
Manufacturer Part Number
EP4SGX530HH35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
Stratix® IV GXr
Datasheets
1.EP4SGX110DF29C3N.pdf
(80 pages)
2.EP4SGX110DF29C3N.pdf
(1154 pages)
3.EP4SGX110DF29C3N.pdf
(432 pages)
4.EP4SGX110DF29C3N.pdf
(22 pages)
5.EP4SGX110DF29C3N.pdf
(30 pages)
6.EP4SGX110DF29C3N.pdf
(72 pages)
7.EP4SGX530HH35C2N.pdf
(1145 pages)
Specifications of EP4SGX530HH35C2N
Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
564
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Family Name
Stratix® IV
Number Of Logic Blocks/elements
531200
# Registers
424960
# I/os (max)
560
Process Technology
40nm
Operating Supply Voltage (typ)
900mV
Logic Cells
531200
Ram Bits
28033024
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FCHBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Manufacturer
Quantity
Price
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5–34
Stratix IV Device Handbook Volume 2: Transceivers
■
■
Consider the following scenario:
■
■
■
■
Option 2 is applicable because the design requires the individual transceiver channels
to be reconfigured with different data rates to another Basic or Protocol functional
mode with rate matching. Therefore, each channel can be reconfigured to another
Basic or Protocol functional mode with rate matching enabled and a different data
rate.
Enable this option if you want the individual transmitter channel’s tx_clkout
signal to provide the read clock to its respective Receive Phase Compensation
FIFO.
This option is typically enabled when all the transceiver channels have rate
matching enabled with different data rates and are reconfigured to another Basic
or Protocol functional mode with rate matching enabled.
TX0/RX0: You want to dynamically reconfigure the Basic 1 Gbps configuration
with rate matching enabled to the Basic 2 Gbps configuration with rate matching
enabled.
TX1/RX1: You want to dynamically reconfigure the Basic 4 Gbps configuration
with rate matching enabled to the Basic 1 Gbps configuration with rate matching
enabled.
TX2/RX2 and TX3/RX3: You want to dynamically reconfigure the Basic
3.125 Gbps configuration with rate matching enabled to the 1 Gbps configuration
with rate matching and vice versa.
Channel and CMU PLL reconfiguration mode is enabled in the
ALTGX_RECONFIG MegaWizard Plug-In Manager.
Option 2: Use the Respective Channel Transmitter Core Clocks
Chapter 5: Dynamic Reconfiguration in Stratix IV Devices
Dynamic Reconfiguration Modes Implementation
February 2011 Altera Corporation
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