EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 842

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

4–36
Dynamic Reconfiguration Reset Sequences
Stratix IV Device Handbook Volume 2: Transceivers
Reset Sequence when Using Dynamic Reconfiguration with the ‘data rate
division in TX’ Option
When using dynamic reconfiguration in data rate divisions in TX or channel and TX
CMU PLL select/reconfig modes, use the following reset sequences.
Use the example reset sequence shown in
reconfiguration controller to change the data rate of the transceiver channel. In this
example, dynamic reconfiguration is used to dynamically reconfigure the data rate of
the transceiver channel configured in Basic ×1 mode with the receiver CDR in
automatic lock mode.
Figure 4–20. Reset Sequence When Using the Dynamic Reconfiguration Controller to Change the
Data Rate of the Transceiver Channel
As shown in
change the configuration of the transmitter channel, follow these reset steps:
1. After power up and properly establishing that the transmitter is operating as
2. Assert the tx_digitalreset signal.
3. As soon as write_all is asserted, the dynamic reconfiguration controller starts to
4. After the completion of dynamic reconfiguration, the busy signal is de-asserted
5. Lastly, tx_digitalreset can be de-asserted to continue with the transmitter
Reset and Control Signals
desired, write the desired new value for the data rate in the appropriate register (in
this example, rate_switch_ctrl[1:0]) and subsequently assert the write_all
signal (marker 1) to initiate the dynamic reconfiguration.
f
execute its operation. This is indicated by the assertion of the busy signal
(marker 2).
(marker 3).
operation (marker 4).
rate_switch_ctrl[1:0]
Ouput Status Signals
tx_digitalreset
For more information, refer to the
Devices
write_all
Figure
busy
chapter.
4–20, when using the dynamic reconfiguration controller to
New value
1
1
2
Chapter 4: Reset Control and Power Down in Stratix IV Devices
Figure 4–20
3
Dynamic Reconfiguration in Stratix IV
4
when you use the dynamic
Dynamic Reconfiguration Reset Sequences
February 2011 Altera Corporation