EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 463

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

Chapter 1: Transceiver Architecture in Stratix IV Devices
Transceiver Block Architecture
Table 1–6. FPGA Fabric-Transceiver Interface Width and Transceiver PMA-PCS Widths (Part 2 of 2)
February 2011 Altera Corporation
Supported functional modes
Data rate range in Basic functional mode
Name
Transmitter Channel Datapath
The transmitter channel datapath, shown in
following blocks:
■
■
■
■
The Stratix IV GX and GT transceiver provides the Enable low latency PCS mode
option in the ALTGX MegaWizard
8B/10B encoder in the datapath is disabled.
TX Phase Compensation FIFO
The TX phase compensation FIFO interfaces the transmitter channel PCS and the
FPGA fabric PCIe interface. It compensates for the phase difference between the
low-speed parallel clock and the FPGA fabric interface clock. The TX phase
compensation FIFO operates in low-latency and high-latency modes.
Figure 1–14
Figure 1–14. TX Phase Compensation FIFO
TX phase compensation FIFO
Byte serializer
8B/10B encoder
Transmitter output buffer
shows the datapath and clocking of the TX phase compensation FIFO.
Data Path from the FPGA
Fabric or PIPE Interface
tx_coreclk
■
■
■
■
■
■
■
PCIe Gen1 and Gen2
XAUI
GIGE
Serial RapidIO
SONET/SDH OC12 and OC48
SDI
Basic single-width
0.6 Gbps to 3.75 Gbps
Single-Width
wr_clk
™
Compensation
Plug-In Manager. If you select this option, the
TX Phase
FIFO
Figure 1–12 on page
rd_clk
Stratix IV Device Handbook Volume 2: Transceivers
Data Path to the Byte Serializer
■
■
■
or the 8B/10B Encoder or
(OIF) CEI PHY Interface
SONET/SDH OC96
Basic double-width
tx_clkout
coreclkout
Serializer
1 Gbps to 8.5 Gbps
Double-Width
1–17, consists of the
1–19