EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 606

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–162
Figure 1–128. Deskew FIFO in XAUI Mode
Note to
(1) This figure is from IEEE P802.3ae.
Stratix IV Device Handbook Volume 2: Transceivers
Figure
1–128:
After alignment of the first ||A|| column, if three additional aligned ||A||
columns are observed at the output of the deskew FIFOs of the four channels, the
rx_channelaligned signal is asserted high, indicating channel alignment is acquired.
After acquiring channel alignment, if four misaligned ||A|| columns are seen at the
output of the deskew FIFOs in all four channels with no aligned ||A|| columns in
between, the rx_channelaligned signal is de-asserted low, indicating loss-of-channel
alignment.
The deskew FIFO operation in XAUI functional mode is compliant with the PCS
deskew state machine diagram specified in clause 48 of the IEEE P802.3ae, as shown
in
Figure
1–128.
(Note 1)
deskew_error * SUDI
deskew_error * SUDI
deskew_error * SUDI
deskew_error * SUDI
deskew_error * SUDI
deskew_error * SUDI
deskew_error * SUDI
SUDI(![/||A||/])
enable_deskew
enable_deskew
AUDI
AUDI
AUDI
AUDI
AUDI
AUDI
AUDI
AUDI
LOSS_OF_ALIGNMENT
enable_deskew
A
B
C
ALIGN_ACQUIRED_1
ALIGN_ACQUIRED_2
ALIGN_ACQUIRED_3
ALIGN_ACQUIRED_4
align_status
ALIGN_DETECT_1
ALIGN_DETECT_2
ALIGN_DETECT_3
SUDI(![/||A||/])
SUDI(![/||A||/])
SUDI(![/||A||/])
SUDI(![/||A||/])
sync_status OK * SUDI(![/||A||/])
⇐
⇐
⇐
⇐
FAIL
FALSE
FALSE
A
B
C
TRUE
Chapter 1: Transceiver Architecture in Stratix IV Devices
SUDI(![/||A||/])
SUDI(![/||A||/])
SUDI(![/||A||/])
reset +
(sync_status=FAIL * SUDI)
!deskew_error
* SUDI(![/||A||/])
!deskew_error
* SUDI(![/||A||/])
!deskew_error
* SUDI(![/||A||/])
!deskew_error
* SUDI(![/||A||/])
!deskew_error
* SUDI(![/||A||/])
!deskew_error
* SUDI(![/||A||/])
!deskew_error
* SUDI(![/||A||/])
February 2011 Altera Corporation
Transceiver Block Architecture