EP4SGX530HH35C2N Altera, EP4SGX530HH35C2N Datasheet - Page 673

• Manufacturer Part Number: EP4SGX530HH35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530HH35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 564
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Family Name: Stratix® IV
• Number Of Logic Blocks/elements: 531200
• # Registers: 424960
• # I/os (max): 560
• Process Technology: 40nm
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 531200
• Ram Bits: 28033024
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FCHBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

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SIV52002-3.2
Figure 2–1. Clocking Architecture Overview
Stratix IV Device Handbook Volume 2: Transceivers
February 2011
February 2011
SIV52002-3.2
This chapter provides detailed information about the Stratix
architecture. For this chapter, the term “Stratix IV devices” includes both
Stratix IV GX and GT devices. Similarly, the term “Stratix IV transceivers” includes
both Stratix IV GX and GT transceivers.
The clocking architecture chapter is divided into three main sections:
■
■
■
Other sections in this chapter include:
Figure 2–1
FPGA
Fabric
“Input Reference Clocking” on page
provided to the clock multiplier unit (CMU)/auxiliary transmit phase-locked loop
(ATX PLL) to generate the clocks required for transceiver operation.
“Transceiver Channel Datapath Clocking” on page
architecture internal to the transceiver block.
“FPGA Fabric-Transceiver Interface Clocking” on page
clocking options available when interfacing the transceiver with the FPGA fabric.
■
■
■
“FPGA Fabric PLLs-Transceiver PLLs Cascading” on page 2–9
“Using the CMU/ATX PLL for Clocking User Logic in the FPGA Fabric” on
page 2–72
“Configuration Examples” on page 2–73
shows an overview of the clocking architecture.
FPGA Fabric-Transciever
Input Reference Clocks
Interface Clocks
2. Transceiver Clocking in Stratix IV
Transceivers
Transceiver Channel Datapath Clocks
CMU/ATX PLL
or CDR
Transceiver Channels
2–2—describes how the reference clock is
2–20—describes the clocking
2–51—describes the
®
IV transceiver clocking
Devices
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